Integrated circuits (ICs) often contain millions of transistors and millions of interconnections. To verify that these transistors and interconnections are manufactured as intended (i.e. defect free), they must be tested. Many testing techniques may be used to verify the operation of an IC.
For example, broadside testing includes electrically stimulating the inputs of an IC and measuring the outputs of the IC to determine if the output matches the predicted output. In the case where the predicted output matches the measured output, the IC may be functioning correctly. However, this test alone does not guarantee that the IC will function 100 percent correctly. More tests are needed to verify that the IC is operating as designed.
In the case where broadside testing is used and the measured output does not match the predicted output, the IC may not be operating correctly. This type of testing indicates that there may be problems with the IC. However, this type of testing usually does not indicate what in particular caused the IC to operate incorrectly. To better diagnose what may be causing the IC to fail, internal scan testing may be used.
Internal scan testing provides a means to test interconnections and transistors without using physical test probes. Internal scan testing usually adds one or more so called ‘test cells’ connected to each pin of an IC that can selectively override the functionality of that pin. These cells can be programmed via a JTAG (Joint Test Action Group) test chain to drive a signal onto a pin and across an individual interconnection. The cell at the destination of the interconnection can then be programmed to read the value at the pin, verifying that the IC trace properly connects the two pins. If the trace is shorted to another signal or if the trace has been cut, the correct signal value may not be presented at the destination pin, and the IC will be observed to have a fault.
In addition to providing a means to test interconnections and transistors without using physical test probes, internal scan testing provides the means for testing delay paths on an integrated circuit. Delay fault (“at-speed” or “cycle-by-cycle”) testing is a test methodology used to measure the time required for a signal to travel through a delay path in logic block or a memory array on an integrated circuit. This time is often called the delay time Td. Usually, the highest frequency Fmax at which an integrated circuit may operate is determined by the longest delay time Td on the integrated circuit. In this case, the highest clock frequency that the integrated circuit may operate is Fmax=1/Td.
Because test cells can be used to force data into an IC, they may be used to set up test patterns. The relevant electronic states (ones and zeros) created as a result of the test patterns, may then be fed back into a test system to verify the functionality of a part of an IC. By adopting this technique, it is possible for a test system to gain test access to many parts of an IC. However, testing a pipelined memory using internal scan testing can be complex due to the read latency of the pipelined memory.
A pipeline with respect to a computer is the continuous and somewhat overlapped movement of data to a processor. Pipelining is the use of a pipeline. Without a pipeline, a computer processor gets the first instruction from memory, performs the operation it calls for, and then goes to get the next instruction from memory. While fetching (getting) the instruction, the arithmetic and logic unit (ALU) of the processor is idle. The processor usually has to wait until it gets the next instruction.
With pipelining, a computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can be performed. The staging of instruction fetching is continuous. The result is an increase in the number of instructions executed in a given time period.
Pipelines and pipelining also apply to computer memory controllers and moving data through various memory staging places. Data may be pipelined (written or read) to banks of memory when the memory addresses have some order. For example, writing or reading data that have consecutive addresses allows data to be pipelined from different memory banks. However, when a non-sequential read or write occurs, data pipelining is interrupted and the full access time of the memory is required to complete the read or write of the memory. The access time may be 3 or 4 clock cycles for example.
Because the read latency of a pipelined memory can be one or more clock cycles, internal scan testing of the pipelined memory can be complex. Testing the read latency of a pipelined memory is important to ensure that a pipelined memory is operable.